As part of the design team, you will be responsible for the 7nm high speed physical designs and working with 3rd party design services to implement and verify. You will be directly involved in the methodology & flow development of Physical Design and Timing Closure for custom and semi-custom blocks. You will also be involved with floorplanning including multi-power domain, PG planning etc. as well as physical implementation of blocks and top-level including clock-tree. You will perform physical verification, timing closure and formal verification for blocks and top-level as well as static and dynamic IR drop analysis, signal, and power EM checks. You will be interfacing with internal and external teams including Design, IP, Library as well as interfacing with 3rd party Design Services company to ensure physical design achieves the best QoR.
Qualifications
Minimum:
• MS in EE/CS with 8-10 years of previous experience.
• Exposure on ASIC design, layout, and semiconductor device/process through previous work/intern experience or course work.
• Experience with scripting/programming using Tcl/Tk/Perl.
• Detail-oriented, self-motivated team worker, with good verbal and written communication skills.
Desired:
• Previous experience in the physical design and automatic place and route is a plus. i.e., Knowledge of Synopsys/Cadence P&R tools.
• Previous experience with custom layout and physical verification is a plus.
• Previous experience in synthesis/STA/FV is a plus.