ASIC Design Verification Engineer

Skills Needed:

• Experience in SoC verification cycle from architecture to tape out to bring up.
• Good knowledge of verification methodologies such as UVM/OVM etc.
• Hand on ASIC-SoC Design verification tests and debug experience.
• Fluency with SystemVerilog randomization constraints, coverage, and assertions methodology
• Good problem-solving skills, and the passion to take on challenges (particularly in AI domain).
• Good experience with SystemVerilog, and verification methodology (UVM/OVM/VMM)
• Experience with C/C++, SystemC (a big plus!)
• Successfully leading the creation/implementation of multiple SoC verification environments and tape-out efforts will be plus. Education & Experience
• MS (EE or CS) or equivalent with multi-year relevant experience.
• Passionate about AI and thriving in a fast-paced and dynamic startup culture.